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1 LTC1473 dual powerpath tm switch driver n power path management for systems with multiple dc sources n all n-channel switching to reduce power losses and system cost n switches and isolates sources up to 30v n adaptive high voltage step-up regulator for n-channel gate drive n capacitor inrush and short-circuit current limited n user-programmable timer to limit switch dissipation n small footprint: 16-pin narrow ssop the ltc ? 1473 provides a power management solution for single and dual battery notebook computers and other portable equipment. the LTC1473 drives two sets of back- to-back n-channel mosfet switches to route power to the input of the main system switching regulator. an internal boost regulator provides the voltage to fully enhance the logic level n-channel mosfet switches. the LTC1473 senses current to limit surge currents both into and out of the batteries and the system supply capacitor during switch-over transitions or during fault conditions. a user-programmable timer monitors the time the mosfet switches are in current limit and latches them off when the programmed time is exceeded. a unique 2-diode mode logic ensures system start-up regardless of which input receives power first. n notebook computers n portable instruments n handi-terminals n portable medical equipment n portable industrial control equipment powerpath is a trademark of linear technology corporation. , ltc and lt are registered trademarks of linear technology corporation. in1 in2 diode timer v + v gg sw gnd ga1 sab1 gb1 sense + sense ga2 sab2 gb2 LTC1473 c out r sense 0.04 w 1 m f 1 m f mmbd914lti 1mh* si9926dy mmbd2838lti 1473 ta01 bat1 dcin bat2 input of system high efficiency dc/dc switching regulator (ltc1735, etc) from power management m p c timer 4700pf mbrd340 si9926dy *coilcraft 1812ls-105xkbc 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 features descriptio u applicatio s u typical applicatio n u
2 LTC1473 absolute m axi m u m ratings w ww u dcin, bat1, bat2 supply voltage .............. C 0.3 to 32v sense + , sense C , v + .................................. C 0.3 to 32v ga1, gb1, ga2, gb2 ................................... C 0.3 to 42v sab1, sab2 ................................................. C 0.3 to 32v sw, v gg ...................................................... C 0.3 to 42v in1, in2, diode ........................................ C 0.3v to 7.5v junction temperature (note 2) ............................. 125 c operating temperature range commercial ............................................. 0 c to 70 c industrial ........................................... C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number package/order i n for m atio n w u u LTC1473cgn LTC1473ign top view gn package 16-lead narrow plastic ssop 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 in1 in2 diode timer v + v gg sw gnd ga1 sab1 gb1 sense + sense ga2 sab2 gb2 t jmax = 125 c, q ja = 150 c/ w symbol parameter conditions min typ max units v + supply operating range 4.75 30 v i s supply current v in1 = v diode = 5v, v in2 = 0v, v sense + = v sense C = 20v l 100 200 m a v gs v gs gate supply voltage v gs = v gg C v + l 7.5 8.5 9.5 v v + uvlo v + undervoltage lockout threshold v + ramping down 2.7 3.1 3.5 v v + uvlohys v + undervoltage lockout hysteresis 0.75 1 1.25 v v hidigin digital input logic high l 2 1.6 v v lodigin digital input logic low l 1.5 0.8 v i in input current v in1 = v in2 = v diode = 5v 1 m a v gs(on) gate-to-source on voltage i ga1 = i ga2 = i gb1 = i gb2 = C 1 m a, v sab1 = v sab2 = 20v l 5.0 5.7 7.0 v v gs(off) gate-to-source off voltage i ga1 = i ga2 = i gb1 = i gb2 = 100 m a, v sab1 = v sab2 = 20v l 00.4 v i bsense + sense + input bias current v sense + = v sense C = 20v l 24.56.5 m a v sense + = v sense C = 0v (note 3) l C 300 C 160 C 100 m a i bsense C sense C input bias current v sense + = v sense C = 20v l 24.56.5 m a v sense + = v sense C = 0v (note 3) l C 300 C 160 C 100 m a v sense inrush current limit sense voltage v sense C = 20v (v sense + C v sense C ) l 0.15 0.20 0.25 v v sense C = 0v (v sense + C v sense C ) 0.10 0.20 0.30 v i pdsab sab1, sab2 pull-down current v in1 = v in2 = v diode = 0.8v 5 20 35 m a v in1 = v in2 = 0.8v, v diode = 2v 30 200 350 m a i timer timer source current v in1 = 0.8v, v in2 = v diode = 2v, v timer = 0v, l 35.59 m a v sense + C v sense C = 300mv v timer timer latch threshold voltage v in1 = 0.8v, v in2 = v diode = 2v l 1.1 1.2 1.3 v t on gate drive rise time c gs = 1000pf, v sab1 = v sab2 = 0v (note 4) 33 m s t off gate drive fall time c gs = 1000pf, v sab1 = v sab2 = 20v (note 4) 2 m s t d1 gate drive turn-on delay c gs = 1000pf, v sab1 = v sab2 = 0v (note 4) 22 m s t d2 gate drive turn-off delay c gs = 1000pf, v sab1 = v sab2 = 20v (note 4) 1 m s f ovgg v gg regulator operating frequency 30 khz electrical characteristics test circuit, v + = 20v, unless otherwise specified. consult factory for military grade parts. (note 1) the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. gn part marking 1473 1473i
3 LTC1473 typical perfor m a n ce characteristics u w dc supply current vs supply voltage supply voltage (v) 0 supply current ( m a) 80 120 40 1473 g01 40 0 10 20 30 5 15 25 35 160 60 100 20 140 v diode = v in1 = 5v v in2 = 0v v diode = 5v v in1 = v in2 = 0v v sense + = v sense = v + dc supply current vs v sense dc supply current vs temperature temperature ( c) ?0 50 supply current ( m a) 60 80 90 100 0 140 1473 g02 70 25 25 50 75 100 125 110 120 130 v + = 20v v diode = v in1 = 5v v in2 = 0v v diode = 5v v in1 = v in2 = 0v v gs gate-to-source on voltage vs temperature temperature ( c) ?0 5.1 v gs gate-to-source on voltage (v) 5.2 5.4 5.5 5.6 0 6.0 1473 g04 5.3 25 25 50 75 100 125 5.7 5.8 5.9 v + = v sab =20v temperature ( c) ?0 1.0 supply voltage (v) 1.5 2.5 3.0 3.5 0 5.5 1473 g05 2.0 25 25 50 75 100 125 4.0 4.5 5.0 start-up threshold shutdown threshold undervoltage lockout threshold (v + ) vs temperature note 4: gate turn-on and turn-off times are measured with no inrush current limiting, i.e., v sense = 0v. gate rise times are measured from 1v to 4.5v and fall times are measured from 4.5v to 1v. delay times are measured from the input transition to when the gate voltage has risen or fallen to 3v. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: t j = t a + (p d )(150 c/w) note 3: i s increases by the same amount as i bsense + + i bsense C when their common mode falls below 5v. electrical characteristics v gs gate supply voltage vs temperature temperature ( c) ?0 8.1 v gs gate supply voltage (v) 8.2 8.4 8.5 8.6 0 9.0 1473 g03 8.3 25 25 50 75 100 125 8.7 8.8 8.9 v + = 20v v gs = v gg ?v + |v sense | common mode(v) 0 supply current ( a) 20 1473 ?tpc02.5 5 10 15 2.5 7.5 12.5 17.5 500 450 400 350 300 250 200 150 100 v + = 20v v diode = v in1 = 5v v in2 = 0v v sense + ?v sense = 0v
4 LTC1473 typical perfor m a n ce characteristics u w logic input threshold voltage vs temperature temperature ( c) ?0 1.0 logci input threshold voltage (v) 1.1 1.3 1.4 1.5 0 1.9 1473 g11 1.2 25 25 50 75 100 125 1.6 1.7 1.8 v high v low v + = 20v logic input threshold voltage vs temperature temperature ( c) ?0 1.0 logic input threshold voltage (v) 1.1 1.3 1.4 1.5 0 1.9 1473 g10 1.2 25 25 50 75 100 125 1.6 1.7 1.8 v high v low v + = 5v timer latch threshold voltage vs temperature temperature ( c) ?0 1.10 timer latch threshold voltage (v) 1.12 1.16 1.18 1.20 0 1.28 1473 g12 1.14 25 25 50 75 100 125 1.22 1.24 1.26 v + = 20v timer source current vs temperature temperature ( c) ?0 4.0 timer source current ( m a) 4.5 5.5 6.0 6.5 0 8.5 1473 g13 5.0 25 25 50 75 100 125 7.0 7.5 8.0 v + = 20v timer = 0v turn-on delay and gate rise time vs temperature temperature ( c) ?0 0 turn-on delay and gate rise time ( m s) 5 15 20 25 0 45 1473 g06 10 25 25 50 75 100 125 30 35 40 gate rise time v + = 20v c load = 1000pf v sab = 0v turn-on delay turn-off delay and gate fall time vs temperature temperature ( c) ?0 0.4 turn-off delay and gate fall time ( m s) 0.6 1.0 1.2 1.4 0 2.2 1473 g07 0.8 25 25 50 75 100 125 1.6 1.8 2.0 gate fall time v + = 20v c load = 1000pf v sab = 20v turn-off delay rise and fall time vs gate capacitive loading gate capacitive loading (pf) 10 20 rise and fall time ( m s) 30 40 100 1000 10000 1473 g08 10 5 25 35 15 0 rise time v sab = 0v fall time v sab = 20v sense pin source current i bsense vs v sense v sense (v) 0 sense pin current ( a) 20 1473 ?tpc14 5 10 15 2.5 7.5 12.5 17.5 175 150 125 100 75 50 25 0 ?5 v + = 20v v diode = v in1 = 5v v in2 = 0v v sense + ?v sense = 0v
5 LTC1473 pi n fu n ctio n s uuu in1 (pin 1): logic input of gate drivers ga1 and gb1. in1 is disabled when in2 is high or diode is low. in2 (pin 2): logic input of gate drivers ga2 and gb2. in2 is disabled when in1 is high or diode is low. diode (pin 3): 2-diode mode logic input. diode over- rides in1 and in2 by forcing the two back-to-back external n-channel mosfet switches to mimic two diodes. timer (pin 4): fault timer. a capacitor connected from this pin to gnd programs the time the mosfet switches are allowed to be in current limit. to disable this function, pin 4 can be grounded. v + (pin 5): input supply. bypass this pin with at least a 1 m f capacitor. v gg (pin 6): gate driver supply. this high voltage supply is intended only for driving the internal micropower gate drive circuitry. do not load this pin with any external circuitry . bypass this pin with at least 1 m f. sw (pin 7): open drain of an internal n-channel mosfet switch. this pin drives the bottom of the v gg switching regulator inductor which is connected between this pin and the v + pin. gnd (pin 8): ground. ga2, gb2 (pins 11, 9): switch gate drivers. ga2 and gb2 drive the gates of the second back-to-back external n-channel switches. sab2 (pin 10): source return. the sab2 pin is connected to the sources of sw a2 and sw b2. a small pull-down current source returns this node to 0v when the switches are turned off. sense C (pin 12): inrush current input. this pin should be connected directly to the bottom (output side) of the low value current sense resistor in series with the two input power selector switch pairs, sw a1/b1 and sw a2/b2, for detecting and controlling the inrush current into and out of the power supply sources and the output capacitor. sense + (pin 13): inrush current input. this pin should be connected directly to the top (switch side) of the low value current sense resistor in series with the two input power selector switch pairs, sw a1/b1 and sw a2/b2, for detecting and controlling the inrush current into and out of the power supply sources and the output capacitor. cur- rent limit is invoked when (v sense + C v sense C ) exceeds 0.2v. ga1, gb1 (pins 16, 14): switch gate drivers. ga1 and gb1 drive the gates of the first back-to-back external n-channel switches. sab1 (pin 15): source return. the sab1 pin is connected to the sources of sw a1 and sw b1. a small pull-down current source returns this node to 0v when the switches are turned off.
6 LTC1473 fu n ctio n al diagra uu w ga1 sab1 gb1 ga2 sab2 gb2 1473 fd sense + sense in1 in2 diode v + timer v + sw to gate drivers v gg gnd 1.20v v gg switching regulator inrush current sense 900k 5.5 a latch r s + sw a1/b1 gate drivers sw a2/b2 gate drivers 16 15 14 13 12 11 10 9 8 6 5 4 3 2 1 7
7 LTC1473 the LTC1473 is responsible for low-loss switching and isolation at the front end of the power management system, where up to two battery packs can be connected and disconnected seamlessly. smooth switching between input power sources is accomplished with the help of lowloss n-channel switches. they are driven by special gate drive circuitry which limits the inrush current in and out of the battery packs and the system power supply capacitors. all n-channel switching the LTC1473 drives external back-to-back n-channel mosfet switches to direct power from two sources: the primary battery and the secondary battery or a battery and a wall unit. (n-channel mosfet switches are more cost effective and provide lower voltage drops than their p- channel counterparts.) gate drive (v gg ) power supply the gate drive for the low-loss n-channel switches is supplied by an internal micropower boost regulator which is regulated at approximately 8.5v above v + , up to 37v maximum. in two battery systems, the LTC1473 v + pin is diode ored through three external diodes connected to the three main power sources, dcin, bat1 and bat2. thus, v gg is regulated at 8.5v above the highest power source and will provide the overdrive required to fully enhance the mosfet switches. for maximum efficiency the top of the boost regulator inductor is connected to v + as shown in figure 1. c1 provides filtering at the top of the 1mh switched inductor, l1, which is housed in a small surface mount package. an internal diode directs the current from the 1mh inductor to the v gg output capacitor c2. inrush and short-circuit current limiting the LTC1473 uses an adaptive inrush current limiting scheme to reduce current flowing in and out of the two main power sources and the following systems input capacitor during switch-over transitions. the voltage across a single small valued resistor, r sense , is measured to ascertain the instantaneous current flowing through the figure 2. sw a1/b1 inrush current limiting v sense + v sense ga1 gb1 sab1 sw a1 sw b1 r sense 1473 f02 bat1 + output load c out v gg LTC1473 6v 6v 200mv threshold sw a/b gate drivers bidirectional inrush current sensing and limiting bat1 bat2 dcin v + sw gnd 1473 f01 v gg l1 1mh c1 1 f 50v to gate drivers (8.5v + v + ) LTC1473 c2 1 f 50v v gg switching regulator figure 1. v gg switching regulator two switch pairs, sw a1/b1 and sw a2/b2, during the transitions. figure 2 shows a block diagram of a switch driver pair, sw a1/b1. a bidirectional current sensing and limiting circuit determines when the voltage drop across r sense reaches 200mv. the gate-to-source voltage, v gs , of the appro- priate switch is limited during the transition period until the inrush current subsides, generally within a few milli- seconds, depending upon the value of the following systems input capacitor. this scheme allows capacitors and mosfet switches of differing sizes and current ratings to be used in the same system without circuit modifications. operatio n u
8 LTC1473 after the transition period, the v gs of both mosfets in the selected switch pair rises to approximately 5.6v. the gate drive is set at 5.6v to provide ample overdrive for standard logic-level mosfet switches without exceeding their maximum v gs rating. in the event of a fault condition the current limit loop will limit the inrush current into the short. at the instant the mosfet switch is in current limit, i.e., when the voltage drop across r sense is 200mv, a fault timer will start timing. it will continue to time as long as the mosfet switch is in current limit. eventually the preset time will lapse and the mosfet switch will latch off. the latch is reset by deselecting the gate drive input. fault time-out is programmed by an external capacitor connected between the timer pin and ground. power path switching concepts power source selection the LTC1473 drives low-loss switches to direct power in the main power path of a single or dual rechargeable battery system, the type found in many notebook comput- ers and other portable equipment. figure 3 is a conceptual block diagram that illustrates the main features of an LTC1473 dual battery power manage- ment system starting with the three main power sources and ending at the output load (i.e.: system dc/dc regulator). switches sw a1/b1 and sw a2/b2 direct power from either batteries to the input of the dc/dc switching regu- lator. each of the switches is controlled by a ttl/cmos compatible input that can interface directly with a power management system m p. using tantalum capacitors the inrush (and outrush) current of the system dc/dc regulator input capacitor is limited by the LTC1473, i.e., the current flowing both in and out of the capacitor during transitions from one input power source to another is limited. in many applications, this inrush current limiting makes it feasible to use smaller tantalum surface mount capacitors in place of larger aluminum electrolytics. note: the capacitor manufacturer should be consulted for specific inrush current specifications and limitations and some experimentation may be required to ensure compli- ance with these limitations under all possible operating conditions. back-to-back switch topology the simple spst switches shown in figure 3 actually consist of two back-to-back n-channel switches. these low-loss n-channel switch pairs are housed in 8-pin so and ssop packaging and are available from a number of manufacturers. the back-to-back topology eliminates the problems associated with the inherent body diodes in power mosfet switches and allows each switch pair to applicatio n s i n for m atio n wu u u figure 3. LTC1473 powerpath conceptual diagram bat1 bat2 inrush current limiting sw a1/b1 sw a2/b2 + high efficiency dc/dc switching regulator 5v 3.3v 1473 f03 12v c in dcin power management m p output load LTC1473
9 LTC1473 applicatio n s i n for m atio n wu u u block current flow in either direction when both switches are turned off. the back-to-back topology also allows for independent control of each half of the switch pair which facilitates bidirectional inrush current limiting and the so-called 2-diode mode described in the following section. the 2-diode mode under normal operating conditions, both halves of each switch pair are turned on and off simultaneously. for example, when the input power source is switched from bat1 to bat2 in figure 4, both gates of switch pair sw a1/b1 are normally turned off and both gates of switch pair sw a2/b2 are turned on. the back-to-back body diodes in switch pair, sw a1/b1, block current flow in or out of the bat1 input connector. in the 2-diode mode, only the first half of each power path switch pair, i.e., sw a1 and sw a2, are turned on; and the second half, i.e., sw b1 and sw b2 are turned off. these two switch pairs now act simply as two diodes connected to the two main input power sources as illus- trated in figure 4. the power path diode with the highest input voltage passes current through to the output load (i.e. input of the dc/dc converter) to ensure that the power management m p is powered even under start-up or abnor- mal operating conditions. (an undervoltage lockout circuit defeats this mode when the v + pin drops below approxi- mately 3.2v. the supply to v + comes from the main power sources, dcin, bat1 and bat2 through three external diodes as shown in figure 1.) the 2-diode mode is asserted by applying an active low to the diode input. component selection n-channel switches the LTC1473 adaptive inrush current limiting circuitry permits the use of a wide range of logic-level n-channel mosfet switches. a number of dual, low r ds(on) n-channel switches in 8-lead surface mount packages are available that are well suited for LTC1473 applications. the maximum allowable drain-source voltage, v ds(max) , of the two switch pairs, sw a1/b1 and sw a2/b2 must be high enough to withstand the maximum dc supply volt- age. if the dc supply is in the 20v to 28v range, use 30v mosfet switches. if the dc supply is in the 10v to 18v range, and is well regulated, then 20v mosfet switches will suffice. figure 4. LTC1473 powerpath switches in 2-diode mode bat1 dcin bat2 sw a2 sw b2 on off r sense high efficiency dc/dc switching regulator 5v 3.3v 1473 f04 12v power management m p + c in sw a1 sw b1 on off LTC1473 output load
10 LTC1473 applicatio n s i n for m atio n wu u u as a general rule, select the switch with the lowest r ds(on) and able to withstand the maximum allowable v ds . this will minimize the heat dissipated in the switches while increasing the overall system efficiency. higher switch resistances can be tolerated in some systems with lower current requirements, but care should be taken to ensure that the power dissipated in the switches is never allowed to rise above the manufacturers recommended level. inrush current sense resistor, r sense a small valued sense resistor (current shunt) is used by the two switch pair drivers to measure and limit the inrush or short-circuit current flowing through the conducting switch pair. the inrush current limit should be set at approximately 2 or 3 the maximum required output current. for example, if the maximum current required by the dc/dc converter is 2a, an inrush current limit of 6a is set by selecting a 0.033 w sense resistor, r sense , using the following for- mula: r sense = (200mv)/i inrush note that the voltage drop across the resistor in this example is only 66mv under normal operating conditions. therefore, the power dissipated in the resistor is ex- tremely small (132mw), and a small 1/4w surface mount resistor can be used in this application (the resistor will tolerate the higher power dissipation during current limit for the duration of the fault time-out). a number of small valued surface mount resistors are available that have been specifically designed for high efficiency current sensing applications. programmable fault timer capacitor, c timer a fault timer capacitor, c timer , is used to program the time duration the mosfet switches are allowed to be in con- tinuous current limit. in the event of a fault condition, the mosfet switch is driven into current limit by the inrush current limit loop. the mosfet switch operating in current limit is in a high dissipation mode and can fail catastrophically if not promptly terminated. the fault time delay is programmed with an external capacitor between the timer pin and gnd. at the instant the mosfet switch enters current limit, a 5.5 m a current source starts charging c timer through the timer pin. when the voltage across c timer reaches 1.2v an internal latch is set and the mosfet switch is turned off. to reset the latch, the logic input of the mosfet gate driver is deselected. the fault time delay should be programmed as large as possible, at least 3 to 5 the maximum switching transi- tion period, to avoid prematurely tripping the protection circuit. conversely, for the protection circuit to be effec- tive, the fault time delay must be within the safe operating area of the mosfet switches, as stated in the manufacturers data sheet. the maximum switching transition period happens during a cold start, when a fully charged battery is connected to an unpowered system. the inrush current charging the system supply capacitor to the battery voltage determines the switching transition period. the following example illustrates the calculation of c timer. assume the maximum battery voltage is 20v, the system supply capacitor is 68 m f, the inrush current limit is 6a and the maximum current required by the dc/dc converter is 2a. then, the maximum switching transition period is calculated using the following formula: t sw(max) = (v bat(max) )(c in(dc/dc) ) i inrush ?i load t sw(max) = = 340 m s (20)(68 m f) 6a ?2a multiplying 3 by 340 m s gives 1.02ms, the minimum fault delay time. make sure this delay time does not fall outside of the safe operating area of the mosfet switch dissipat- ing 60w (6a ? 20v/2). using this delay time the c timer can be calculated using the following formula: c timer = 1.02ms = 4700pf 5.5 m a 1.20v ) ) therefore, c timer should be 4700pf.
11 LTC1473 applicatio n s i n for m atio n wu u u v gg regulator inductor and capacitors the v gg regulator provides a power supply voltage 8.5v higher than any of the three main power source voltages to allow the control of n-channel mosfet switches. this micropower, step-up voltage regulator is powered by the highest potential available from the three main power sources for maximum regulator efficiency. bat1 bat2 dcin v gg switching regulator v + sw gnd 1473 f05 v gg l1* 1mh c1 1 f 50v c2 1 f 50v to gate drivers (8.5v + v + ) LTC1473 *coilcraft 1812ls-105 xkbc. (708) 639-6400 figure 5. v gg step-up switching regulator three external components are required by the v gg regu- lator: l1, c1 and c2, as shown in figure 5. l1 is a small, low current, 1mh surface mount inductor. c1 provides filtering at the top of the 1mh switched inductor and should be at least 1 m f to filter switching transients. the v gg output capacitor, c2, provides storage and filter- ing for the v gg output and should be at least 1 m f and rated for 50v operation. c1 and c2 can be ceramic capacitors.
12 LTC1473 typical applicatio n s u l1* 1mh c timer 4700pf c timer 4700pf power management p r sense 0.033 w smbus bat2 8.4v li-ion bat1 12v nicd 750k battery charger dcin mbrd340 mmbd914lt1 * coilcraft 1812ls-105xkbc c7 1 m f c8 1 m f 500k timer v + v gg sw gnd ga1 sab1 gb1 sense + sense ga2 sab2 gb2 LTC1473 si9926dy si9926dy mmbd2838lt1 1473 ta02 16 15 14 13 12 11 10 9 4 5 6 7 8 timer v + v gg sw gnd ga1 sab1 gb1 sense + sense ga2 sab2 gb2 LTC1473 16 15 14 13 12 11 10 9 4 5 6 7 8 si9926dy si9926dy in1 in2 1 2 3 diode 1 2 3 in1 in2 diode r sense 0.033 w high efficiency dc/dc switching regulator input power routing circuit for microprocessor controlled dual battery dual chemistry system
13 LTC1473 typical applicatio n s u r sense 0.015 w q1 si4412dy c4 0.1 m f d1 cmdsh-3 c3 4.7 m f 16v d2 mbrs140t3 c in 22 m f 35v 2 c out 100 m f 10v 3 v out 5v/3.5a q2 si4412dy + + r1 105k 1% l1* 10 m h sgnd 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 c1 100pf c5 1000pf c ss , 0.1 m f c c2 , 51pf c osc 57pf r c , 10k c c 330pf + c6 100pf c2, 0.1 m f r2 20k 1% 4700pf c timer c7 1 m f c8 1 m f gnd sw boost gnd gnd uv gnd ovp clp cln comp1 sense gnd gnd v cc1 v cc2 v cc3 prog v c uvout gnd comp2 bat spin lt 1511 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 dcin out a v in + a in b out b v + ref hyst ltc1442 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 1 2 3 4 8 7 6 5 74c00 12 3 4 5 6 13 12 11 14 mmbd2838lt1 d5 mbrd340 c11 0.47 m f d6 mbr0540t d4 mbrd340 l3*** 20 m h 2,3 1,4 c10 1 m f r13 5.1k 1% r12 3k 1% c16 220pf r sense 0.033 w r20 395k 0.1% r21 164k 0.1% c17 10 m f 8.4v li-ion battery r19 200 w 1% r15 1k c15 0.33 m f r16 300 w c14 1 m f r17 4.93k c12 10 m f c13 10 m f r sense 0.033 w r14 510 w r6 900k 1% r7 130k 1% r9 113k 1% r8 427k 1% r10 50k 1% r11 1132k 1% c9 0.1 m f r5 500k 7 l2** 1mh r18, 200 w, 1% 1473 ta03 *sumida cdrh125-10 **coilcraft 1812ls-105xkbc ***coiltronics ctx20-4 10 9 8 si9926dy r sense 0.033 w in1 in2 diode timer v + v gg sw gnd ga1 sab1 gb1 sense + sense ga2 sab2 gb2 LTC1473 si9926dy d3 6.8v tg boost sw v in intv cc bg pgnd extv cc c osc run/ss i th sfb sgnd v osense sense sense + ltc1735 8 + v out complete front end including battery charger and dc/dc converter with automatic switchover between battery and dcin
14 LTC1473 typical applicatio n u protected automatic switchover between two supplies 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 in1 in2 diode timer v + v gg sw gnd ga1 sab1 gb1 sense + sense ga2 sab2 gb2 LTC1473 + l1*, 1mh c5 1 f + c7 1 f c6 4700pf + 5 6 7 + 3 2 1 8 4 1m 1m 10k 10k 1m supply v2 supply v1 1m 1 f 5v 18 3 lt1121-5 d1 mmbd2838lt1 q1 si9926dy q2 si9926dy r3 0.033 out *1812ls-105xkbc, coilcraft 1473 ta04 lt1490
15 LTC1473 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. gn package 16-lead plastic ssop (narrow 0.150) (ltc dwg # 05-08-1641) dimensions in inches (millimeters) unless otherwise noted. package descriptio n u gn16 (ssop) 1098 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side 12 3 4 5 6 7 8 0.229 ?0.244 (5.817 ?6.198) 0.150 ?0.157** (3.810 ?3.988) 16 15 14 13 0.189 ?0.196* (4.801 ?4.978) 12 11 10 9 0.016 ?0.050 (0.406 ?1.270) 0.015 0.004 (0.38 0.10) 45 0 ?8 typ 0.007 ?0.0098 (0.178 ?0.249) 0.053 ?0.068 (1.351 ?1.727) 0.008 ?0.012 (0.203 ?0.305) 0.004 ?0.0098 (0.102 ?0.249) 0.0250 (0.635) bsc 0.009 (0.229) ref
16 LTC1473 1473fas, sn1473 lt/tp 0400 rev a 2k ? printed in usa ? linear technology corporation 1997 related parts part number description comments ltc1155 dual high side micropower mosfet driver internal charge pump requires no external components ltc1161 quad protected high side mosfet driver rugged, designed for harsh environment LTC1473l dual powerpath switch driver low voltage version of the LTC1473; operates with 3.3v input ltc1479 powerpath controller for dual battery systems designed to interface with a power management m p lt1505 synchronous constant-voltage/constant-current up to 6a charge current; high efficiency; adaptive current limiting battery charger lt1510 constant-voltage/constant-current battery charger up to 1.5a charge current for lithium-ion, nicd and nimh batteries lt1511 3a constant-voltage/constant-current battery charger high efficiency, minimal external components to fast charge lithium, nimh and nicd batteries ltc1628 2-phase dual synchronous step-down controller minimum input capacitors; 4.5v v in 36v ltc1735 high efficiency synchronous switching regulator constant frequency, v in 36v, fault protection linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com typical applicatio n s u protected hot swap tm switchover between two supplies hot swap is a trademark of linear technology corporation. 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 in1 in2 diode timer v + v gg sw gnd ga1 sab1 gb1 sense + sense ga2 sab2 gb2 LTC1473 l1*, 1mh c5 1 f c7 1 f 100k 100k c6 4700pf supply v2 12v supply v1 5v d1 mmbd2838lt1 q1 si4936dy q2 si4936dy r3 0.1 out 5v docking connector on long pin long pin short pin *1812ls-105xkbc, coilcraft 1473 ?ta05 other 5v logic supply

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